1. Field of the Invention
The present invention relates to a semiconductor device, a charge pump circuit and a PLL circuit. More particularly, the present invention relates to a semiconductor device, a charge pump circuit and a PLL circuit that can suppress a switching noise.
2. Description of the Related Art
As a conventional charge pump, a technique disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 11-339463) is well known. As shown in FIG. 1, when switching transistors 2, 3 connected to an up signal input terminal 10 and a down signal input terminal 11, respectively, are turned on and off, the parasitic capacitances of the respective transistors 2, 3 cause the voltages of drain terminals 12, 13 of constant current transistors 1, 4 to be different from each other.
For this reason, the current values are different when on-signals are inputted to the up signal input terminal 10 and the down signal input terminal 11, respectively. This difference brings about a generation of an error signal.
In order to solve the above-mentioned problem, conventionally, as shown in FIG. 2, a first condenser 6 is mounted between the drain of the constant current transistor 1 and a positive power supply terminal VDD, a second condenser 7 is mounted between the drain of the constant current transistor 1 and a negative power supply terminal VSS, a third condenser 8 is mounted between the drain of the constant current transistor 4 and the positive power supply terminal VDD, and a fourth condenser 9 is mounted between the drain of the constant current transistor 4 and the negative power supply terminal VSS.
The first and second condensers 6, 7 are used to keep the drain voltage and the source voltage of the switching transistor 2 substantially equal to each other. The third and fourth condensers 8, 9 are used to keep the drain voltage and the source voltage of the switching transistor 3 substantially equal to each other. Here, the condenser capacitances of the first to fourth condensers 6 to 9 are designed to be much larger than the parasitic capacitances on the drain terminals 12, 13 oft e constant current transistors 1, 4.
Accordingly, it is possible to reduce the voltage variations in the drain terminals 12, 13 when the on-signals are inputted to the up signal input terminal 10 and the down signal input terminal 11, respectively, and thereby possible to suppress the error current.
According to the above-mentioned configuration, a relatively large capacitance, such as several pF to several tens of pF, requires a wide area.
Also, the measure for the parasitic capacitances of the switching transistors 2, 3 that cause the switching noise is not carried out, which results in a problem that the switching noise is not suppressed. In the above-mentioned configuration, a switching voltage is 0 to VDD, and this is a very high value. Thus, the high voltage charged in the parasitic capacitance leads to the switching noise.
Further, Japanese Laid Open Patent Application (JP-A-2000-49596) discloses a charge pump circuit used in a PLL circuit. This charge pump circuit turns back a current generated from a constant current source by sing a current mirror circuit, via an analog switch that is always turned on, and in response to an UP signal sent from a frequency/phase comparator, sends/stops a constant current, which is turned ON/OFF by a switching circuit containing an analog switch and copied by a current mirror, towards a loop filter at a latter stage, and similarly in response to a DOWN signal, sends/stop a constant current, which is turned ON/OFF by a switching circuit containing an analog switch and copied by a current mirror, towards a loop filter at a latter stage.
A charge pump is desired for suppressing a switching noise, in particular, for suppressing a switching noise without the necessity for a wide area.
A charge pump is desired for suppressing a switching noise without any necessity of a wide area.
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide a semiconductor device, a charge pump and a PLL circuit which can suppress a switching noise.
Another object of the present invention is to provide a semiconductor device, a charge pump and a PLL circuit which can suppress a switching noise without the necessity for a wide area.
Still another object of the present invention is to provide a semiconductor device, a charge pump and a PLL circuit which can suppress a switching noise and compensate for an error current.
Still another object of the present invention is to provide a semiconductor device, a charge pump and a PLL circuit which can suppress a switching noise without the necessity for a wide area and compensate for an error current.
In order to achieve an aspect of the present invention, a semiconductor device, includes: first and second output stage transistors generating an output signal as a result of a push-pull operation, which are mutually connected in series between a first power supply and a second power supply; a first transistor that has a control electrode, to which a first input signal is inputted, and is connected between the first power supply and the second power supply; a first constant current source connected in series to the first transistor between the first power supply and the second power supply; a first specific transistor which is connected in series to the first transistor and the first constant current source between the first power supply and the second power supply and connected as current mirror to the first output stage transistor; a second transistor that has a control electrode, to which a second input signal is inputted, and is connected between the first power supply and the second power supply; a second constant current source that is connected in series to the second transistor between the first power supply and the second power supply; and a second specific transistor which is connected in series to the second transistor and the second constant current source between the first power supply and the second power supply and connected as current mirror to the second output stage transistor.
In this case, the semiconductor device further includes: a current error compensation circuit compensating for errors of currents respectively flowing through the first and second output stage transistors at the time of the push-pull operation, in accordance with the output signal and a reference signal.
Also in this case, the first transistor and the second transistor are MOS-type transistors.
In order to achieve another aspect of the present invention, a charge pump circuit that is used in a PLL (Phase-Locked Loop) circuit, and generates an output signal in response to an up instruction signal and a down instruction signal sent from a phase comparator to drive a VCO (Voltage-Controlled Oscillator) in accordance with the output signal, includes: first and second output stage transistors generating the output signal as a result of a push-pull operation, which are mutually connected in series between a first power supply and a second power supply; a first transistor that has a control electrode, to which the up instruction signal is inputted, and is connected between the first power supply and the second power supply; a first constant current source that is connected in series to the first transistor between the first power supply and the second power supply; a first specific transistor which is connected in series to the first transistor and the first constant current source between the first power supply and the second power supply and connected as current mirror to the first output stage transistor; a second transistor that has a control electrode, to which an inversion signal of the down instruction signal is inputted, and is connected between the first power supply and the second power supply; a second constant current source that is connected in series to the second transistor between the first power supply and the second power supply; and a second specific transistor which is connected in series to the second transistor and the second constant current source between the first power supply and the second power supply and connected as current mirror to the second output stage transistor.
In this case, the charge pump circuit further includes: a current error compensation circuit compensating for errors of currents respectively flowing through the first and second output stage transistors at the time of the push-pull operation, in accordance with the output signal and a reference signal.
Also in this case, the first transistor and the second transistor are MOS-type transistors.
In order to achieve still another aspect of the present invention, a PLL (Phase-Locked Loop) circuit includes: a phase comparator; a VCO (Voltage Controlled Oscillator); and a charge pump circuit generating an output signal in response to an up instruction signal and a down instruction signal sent from the phase comparator to drive the VCO based on the output signal, and wherein the charge pump circuit includes: first and second output stage transistors generating the output signal as a result of a push-pull operation, which are mutually connected in series between a first power supply and a second power supply; a first transistor that has a control electrode, to which the up instruction signal is inputted, and is connected between the first power supply and the second power supply; a first constant current source that is connected in series to the first transistor between the first power supply and the second power supply; a first specific transistor which is connected in series to the first transistor and the first constant current source between the first power supply and the second power supply and connected as current mirror to the first output stage transistor; a second transistor that has a control electrode, to which an inversion signal of the do n instruction signal is inputted, and is connected between the first power supply and the second power supply; a second constant current source that is connected in series to the second transistor between the first power supply and the second power supply; and a second specific transistor which is connected in series to the second transistor and the second constant current source between the first power supply and the second power supply and connected as current mirror to the second output stage transistor.
In this case, the PL circuit further includes: a current error compensation circuit compensating for errors of currents respectively flowing through the first and second output stage transistors at the time of the push-pull operation, in accordance with the output signal and a reference signal.
Also in this case, the first transistor and the second transistor are MOS-type transistors.
In order to achieve et still another aspect of the present invention, a semiconductor device includes: first and second output stage transistors generating a first output signal as a result of a push-pull operation, which are mutually connected in series between a first power supply and a second power supply; third and fourth output stage transistors generating a second output signal as a result of a push-pull operation, which are mutually connected in series between the first power supply and the second power supply; first and second differential transistor pairs that conductive types are opposite to each other and have control electrodes connected to first and second input terminals, respectively; first and second constant current sources connected to the first and second differential transistor pairs, respectively; a first current mirror circuit connected between the first differential transistor pairs and the first power supply; a second current mirror circuit connected between the second differential transistor pairs and the second power supply; third and fourth differential transistor pairs that conductive types are opposite to each other and have control electrodes connected to third and fourth input terminals, respectively; third and fourth constant current sources connected to the third and fourth differential transistor pairs, respectively; a third current mirror circuit connected between the third differential transistor pairs and the first power supply; and a fourth current mirror circuit connected between the fourth differential transistor pairs and the second power supply, and wherein the first output stag transistor is included in the first current mirror circuit, and wherein the second output stage transistor is included in the fourth current mirror circuit, and wherein the third output stage transistor is included in the third current mirror circuit and wherein the fourth output stage transistor is included in the second current mirror circuit.
In this case, the semiconductor device further includes: a current error compensation circuit compensating for errors of currents respectively flowing through the first and second output stage transistors at the time of the push-pull operation, in accordance with the output signal and a reference signal.
In order to achieve another aspect of the present invention, a charge pump circuit that is used in a PLL (Phase-Locked Loop) circuit, and generates a first output signal and a second output signal in which the first output signal is inverted, in response to an up instruction signal and a down instruction signal sent from a phase comparator to drive a VCO (Voltage-Controlled Oscillator) in accordance with the first and second output signals, includes: first and second output stage transistors generating the first output signal as a result of a push-pull operation, which are mutually connected in series between a first power supply and a second power supply; third and fourth output stage transistors generating the second output signal as a result of a push-pull operation, which are mutually connected in series between the first power supply and the second power supply; first and second differential transistor pairs that conductive types are opposite to each other and have control electrodes connected to first and second input terminals, respectively, to which the up instruction signal and an up instruction inversion signal where the up instruction signal is inverted are sent; first and second constant current sources connected to the first and second differential transistor pairs, respectively; a first current mirror circuit connected between the first differential transistor pairs and the first power supply; a second current mirror circuit connected between the second differential transistor pairs and the second power supply; third and fourth differential transistor pairs that conductive types are opposite to each other and have a control electrode connected to third and fourth input terminals, respectively, to which the down instruction signal and a down instruction inversion signal where the down instruction signal is inverted are sent; third and fourth constant current sources connected to the third and fourth differential transistor pairs, respectively; a third current mirror circuit connected between the third differential transistor pairs and the first power supply; and a fourth current mirror circuit connected between the fourth differential transistor pairs and the second power supply, and wherein the first output stage transistor is included in the first current mirror circuit, and wherein the second output stage transistor is included in the fourth current mirror circuit, and wherein the third output stage transistor is included in the third current mirror circuit and wherein the fourth output stage transistor is included in the second current mirror circuit.
In this case, the charge pump circuit further includes: a current error compensation circuit compensating for errors of currents flowing through the first to fourth mirror circuits, respectively.
Also in this case, the charge pump circuit, further includes: fifth and sixth constant current sources connected in parallel to the first and third constant current sources, respectively; and wherein the current error compensation circuit generates a control signal corresponding to a difference between a set signal and a signal indicative of an average value between the first and second output signals, and wherein the fifth and sixth constant current sources change values of currents to be sent to the first and third differential transistor pairs, in response to the control signal.
In order to achieve till another aspect of the present invention, a PLL (Phase-Locked Loop) circuit includes: a phase comparator; a VCO (Voltage-Controlled Oscillator); and a charge pump circuit generating a first output signal and a second output signal in which the first output signal is inverted, in response to an up instruction signal and a down instruction signal sent from the phase comparator to drive the VCO in accordance with the first and second output signals, and wherein the charge pump circuit includes: first and second output stage transistors generating the first output signal as a result of a push-pull operation, which are mutually connected in series between first power supply and a second power supply; third and fourth output stage transistors generating the second output signal as a result of a push-pull operation, which are mutually connected in series between the first power supply and the second power supply; first and second differential transistor pairs that conductive types are opposite to each other and have control electrodes connected to first and second input terminals, respectively, to which the up instruction signal and an up instruction inversion signal where the up instruction signal is inverted are sent; first and second constant current sources connected to the first and second differential transistor pairs, respectively; a first current mirror circuit connected between the first differential transistor pairs and the first power supply; a second current mirror circuit connected between the second differential transistor pairs and the second power supply; third and fourth differential transistor airs that conductive types are opposite to each other and have control electrodes connected to third and fourth input terminals, respectively, to which the down instruction signal and a down instruction inversion signal where the down instruction signal is inverted are sent; third and fourth constant current sources connected to the third and fourth differential transistor pairs, respectively; a third current mirror circuit connected between the third differential transistor pairs and the first power supply; and a fourth current mirror circuit connected between the fourth differential transistor pairs and the second power supply, and wherein the first output stag transistor is included in the first current mirror circuit, and wherein the second output stage transistor is included in the fourth current mirror circuit, and wherein the third output stage transistor is included in the third current mirror circuit and wherein the fourth output stage transistor is included in the second current mirror circuit.
In order to achieve et still another aspect of the present invention, the PLL circuit further includes: a current e or compensation circuit compensating for errors of currents flowing through the first to fourth mirror circuits, respectively.
In the present invention, the charge pump circuit is constituted by using the current mirror in order to suppress the switching noise. Moreover, the error current compensation circuit is used in order to compensate for the error current in the charged case.
The UP, UPB, DOWN and DOWNB signals are inputted from the phase comparator to the differential circuits. The load of the differential circuit is constituted by the current mirror circuit. So, the current flowing through the load is outputted to the filter of the PLL.
Also, the differential circuit has the current error compensation terminal for compensating for the current errors on the UP side and the DOWN side. The operation for compensating for the current error compares a middle value of the capacitance terminal voltages of the respective filters with a reference voltage (ref), and its compared result is fed back to the charge pump (Common Mode Feed Back).